STL features

STL instructions (and current state of support)

STL mnemonic Grammar rule Grammar mnemonic Grammar argument Typing CFA support
+ StlAddIntConstStatement --- NamedOrUnnamedConstantRef + -
= StlAssignStatement --- UnaryOrPrimaryExpression + +
) StlBitLogicNestingCloseStatement --- --- NA +
+AR1 (no address register support yet) --- --- np np
+AR2 (no address register support yet) --- --- np np
+D StlArithmeticStatement PLUS, DINT --- NA +
-D StlArithmeticStatement MINUS, DINT --- NA +
*D StlArithmeticStatement MULTIPLICATION, DINT --- NA +
/D StlArithmeticStatement DIVISION, DINT --- NA -
==D StlComparisonStatement --- --- NA +
<>D StlComparisonStatement --- --- NA +
>D StlComparisonStatement --- --- NA +
<D StlComparisonStatement --- --- NA +
>=D StlComparisonStatement --- --- NA +
<=D StlComparisonStatement --- --- NA +
+I StlArithmeticStatement PLUS, INT --- NA +
-I StlArithmeticStatement MINUS, INT --- NA +
*I StlArithmeticStatement MULTIPLICATION, INT --- NA +
/I StlArithmeticStatement DIVISION, INT --- NA -
==I StlComparisonStatement --- --- NA +
<>I StlComparisonStatement --- --- NA +
>I StlComparisonStatement --- --- NA +
<I StlComparisonStatement --- --- NA +
>=I StlComparisonStatement --- --- NA +
<=I StlComparisonStatement --- --- NA +
+R StlArithmeticStatement PLUS, REAL --- NA +
-R StlArithmeticStatement MINUS, REAL --- NA +
*R StlArithmeticStatement MULTIPLICATION, REAL --- NA +
/R StlArithmeticStatement DIVISION, REAL --- NA -
==R StlComparisonStatement --- --- NA -
<>R StlComparisonStatement --- --- NA -
>R StlComparisonStatement --- --- NA -
<R StlComparisonStatement --- --- NA -
>=R StlComparisonStatement --- --- NA -
<=R StlComparisonStatement --- --- NA -
A StlBitLogicStatement AND UnaryOrPrimaryExpression + +
A( StlBitLogicNestingOpenStatement AND --- NA +
ABS StlFloatMathFunction ABS --- NA -
ACOS StlFloatMathFunction ACOS --- NA -
AD StlWordLogicArglessStatement AND_DWORD --- NA +
AD .. StlWordLogicStatement AND_DWORD --- NA -
AN StlBitLogicStatement AND_NOT UnaryOrPrimaryExpression + +
AN( StlBitLogicNestingOpenStatement AND_NOT --- NA +
ASIN StlFloatMathFunction ASIN --- NA -
ATAN StlFloatMathFunction ATAN --- NA -
AW StlWordLogicArglessStatement AND_WORD --- NA +
AW .. StlWordLogicStatement AND_WORD NamedOrUnnamedConstantRef + -
BE StlBlockEndStatement BLOCK_END --- NA +
BEC StlBlockEndStatement BLOCK_END_CONDITIONAL --- NA +
BEU StlBlockEndStatement BLOCK_END_UNCONDITIONAL --- NA +
BLD StlBldStatement --- UnaryOrPrimaryExpression + +
BTD StlConversionStatement BCD_TO_DINT --- np np
BTI StlConversionStatement BCD_TO_INT --- np np
CAD StlConversionStatement CAD --- np np
CALL StlSubroutineCall --- --- NA +
CALL StlSubroutineCall --- --- NA +
CALL StlSubroutineCall --- --- NA +
CAR (no address register support yet) --- --- np np
CAW StlConversionStatement CAW --- np np
CC StlParameterlessCallStatement CONDITIONAL_CALL --- NA +
CD (no counter/timer support yet) --- --- np np
CDB (no address register support yet) --- --- np np
CLR StlClrRloStatement --- --- NA +
COS StlFloatMathFunction COS --- NA -
CU (no counter/timer support yet) --- --- np np
DEC StlAccuDecrementStatement --- NamedOrUnnamedConstantRef + +
DTB StlConversionStatement DINT_TO_BCD --- NA np
DTR StlConversionStatement DINT_TO_REAL --- NA -
ENT StlAccuArglessStatement ENTER_ACCU_STACK --- NA -
EXP StlFloatMathFunction EXP --- NA -
FN StlFnStatement --- UnaryOrPrimaryExpression + +
FP StlFpStatement --- UnaryOrPrimaryExpression + +
FR (no counter/timer support yet) --- --- np np
FR (no counter/timer support yet) --- --- np np
INC StlAccuIncrementStatement --- NamedOrUnnamedConstantRef + +
INVD StlConversionStatement DINT_ONES_COMPLEMENT --- NA +
INVI StlConversionStatement INT_ONES_COMPLEMENT --- NA +
ITB StlConversionStatement INT_TO_BCD --- NA np
ITD StlConversionStatement INT_TO_DINT --- NA +
JBI StlJumpStatement JUMP_IF_BR_TRUE --- NA +
JC StlJumpStatement JUMP_IF_RLO_TRUE --- NA +
JCB StlJumpStatement JUMP_IF_RLO_TRUE_WITH_BR --- NA +
JCN StlJumpStatement JUMP_IF_RLO_FALSE --- NA +
JL - --- --- --- -
JM StlJumpStatement JUMP_IF_MINUS --- NA +
JMZ StlJumpStatement JUMP_IF_MINUS_OR_ZERO --- NA +
JN StlJumpStatement JUMP_IF_NOT_ZERO --- NA +
JNB StlJumpStatement JUMP_IF_RLO_FALSE_WITH_BR --- NA +
JNBI StlJumpStatement JUMP_IF_BR_FALSE --- NA +
JO StlJumpStatement JUMP_IF_OV_TRUE --- NA -
JOS StlJumpStatement JUMP_IF_OS_TRUE --- NA -
JP StlJumpStatement JUMP_IF_PLUS --- NA +
JPZ StlJumpStatement JUMP_IF_PLUS_OR_ZERO --- NA +
JU StlJumpStatement JUMP_UNCONDITIONAL --- NA +
JUO StlJumpStatement JUMP_IF_UNORDERED --- NA +
JZ StlJumpStatement JUMP_IF_ZERO --- NA +
L StlLoadStatement --- UnaryOrPrimaryExpression + +
L DBLG - --- --- --- -
L DBNO - --- --- --- -
L DILG - --- --- --- -
L DINO - --- --- --- -
L STW StlLoadStwStatement --- --- NA np
L (no counter/timer support yet) --- UnaryOrPrimaryExpression np np
L (no counter/timer support yet) --- UnaryOrPrimaryExpression np np
LAR1 (no address register support yet) --- --- np np
LAR1 <D> (no address register support yet) --- --- np np
LAR1 AR2 (no address register support yet) --- --- np np
LAR2 (no address register support yet) --- --- np np
LAR2 <D> (no address register support yet) --- --- np np
LC (no counter/timer support yet) --- --- np np
LC (no counter/timer support yet) --- --- np np
LEAVE StlAccuArglessStatement LEAVE_ACCU_STACK --- NA -
LN StlFloatMathFunction LN --- NA -
LOOP StlJumpStatement LOOP --- NA -
MCR( StlMcrStatement BEGIN_MCR --- --- np
)MCR StlMcrStatement END_MCR --- --- np
MCRA StlMcrStatement ACTIVATE_MCR --- --- np
MCRD StlMcrStatement DEACTIVATE_MCR --- --- np
MOD StlModStatement --- --- NA +
NEGD StlConversionStatement DINT_TWOS_COMPLEMENT --- NA -
NEGI StlConversionStatement INT_TWOS_COMPLEMENT --- NA -
NEGR StlConversionStatement REAL_NEGATE --- NA -
NOP 0 StlNopStatement --- UnaryOrPrimaryExpression + +
NOP 1 StlNopStatement --- UnaryOrPrimaryExpression + +
NOT StlNegateRloStatement --- --- NA +
O StlBitLogicStatement OR UnaryOrPrimaryExpression + +
O StlAndBeforeOr --- --- NA +
O( StlBitLogicNestingOpenStatement OR --- NA +
OD StlWordLogicArglessStatement OR_DWORD --- NA +
OD .. StlWordLogicStatement OR_DWORD NamedOrUnnamedConstantRef + -
ON StlBitLogicStatement OR_NOT UnaryOrPrimaryExpression + +
ON( StlBitLogicNestingOpenStatement OR_NOT --- NA +
OPN (no address register support yet) --- --- np np
OW StlWordLogicArglessStatement OR_WORD --- NA +
OW .. StlWordLogicStatement OR_WORD NamedOrUnnamedConstantRef + -
POP StlAccuArglessStatement POP_ACCU --- NA -
POP StlAccuArglessStatement POP_ACCU --- NA -
POP StlAccuArglessStatement POP_ACCU --- NA -
PUSH StlAccuArglessStatement PUSH_ACCU --- NA -
PUSH StlAccuArglessStatement PUSH_ACCU --- NA -
R StlResetStatement --- UnaryOrPrimaryExpression + +
R StlResetStatement --- UnaryOrPrimaryExpression np -
R StlResetStatement --- UnaryOrPrimaryExpression np -
RLD StlShiftRotateStatement ROTATE_LEFT_DWORD NamedOrUnnamedConstantRef, optional + -
RLDA StlShiftRotateStatement ROTATE_LEFT_DWORD_VIA_CC1 --- NA -
RND StlConversionStatement ROUND --- NA -
RND– StlConversionStatement RND_MINUS --- NA ?
RND+ StlConversionStatement RND_PLUS --- NA ?
RRD StlShiftRotateStatement ROTATE_RIGHT_DWORD NamedOrUnnamedConstantRef, optional + -
RRDA StlShiftRotateStatement ROTATE_RIGHT_DWORD_VIA_CC1 --- + -
S StlSetStatement --- UnaryOrPrimaryExpression + +
S StlSetStatement --- UnaryOrPrimaryExpression np -
SAVE StlSaveRloStatement --- --- NA +
SD (no counter/timer support yet) --- --- np np
SE (no counter/timer support yet) --- --- np np
SET StlSetRloStatement --- --- NA +
SF (no counter/timer support yet) --- --- np np
SIN StlFloatMathFunction SIN --- NA -
SLD StlShiftRotateStatement SHIFT_LEFT_DWORD --- + -
SLW StlShiftRotateStatement SHIFT_LEFT_WORD --- + -
SP (no counter/timer support yet) --- --- np np
SQR StlFloatMathFunction SQR --- NA -
SQRT StlFloatMathFunction SQRT --- NA -
SRD StlShiftRotateStatement SHIFT_RIGHT_DWORD NamedOrUnnamedConstantRef, optional + -
SRW StlShiftRotateStatement SHIFT_RIGHT_WORD NamedOrUnnamedConstantRef, optional + -
SS (no counter/timer support yet) --- --- np np
SSD StlShiftRotateStatement SHIFT_RIGHT_SIGN_DINT NamedOrUnnamedConstantRef, optional + -
SSI StlShiftRotateStatement SHIFT_RIGHT_SIGN_INT NamedOrUnnamedConstantRef, optional + -
T StlTransferStatement --- UnaryOrPrimaryExpression !!! +
T STW StlTransferStwStatement --- --- NA -
TAK StlAccuArglessStatement TOGGLE_ACCUS --- NA -
TAN StlFloatMathFunction TAN --- NA -
TAR1 (no address register support yet) --- --- np np
TAR1 (no address register support yet) --- --- np np
TAR1 (no address register support yet) --- --- np np
TAR2 (no address register support yet) --- --- np np
TAR2 (no address register support yet) --- --- np np
TRUNC StlConversionStatement TRUNCATE --- NA -
UC StlParameterlessCallStatement UNCONDITIONAL_CALL --- + +
X StlBitLogicStatement XOR UnaryOrPrimaryExpression + +
X( StlBitLogicNestingOpenStatement XOR --- NA +
XN StlBitLogicStatement XOR_NOT UnaryOrPrimaryExpression + +
XN( StlBitLogicNestingOpenStatement XOR_NOT --- NA +
XOD StlWordLogicArglessStatement XOR_DWORD --- NA +
XOD .. StlWordLogicStatement XOR_DWORD NamedOrUnnamedConstantRef + -
XOW StlWordLogicArglessStatement XOR_WORD --- NA +
XOW .. StlWordLogicStatement XOR_WORD NamedOrUnnamedConstantRef + -

(np: implementation not planned)

Missing features

  • Floating point arithmetic not supported (yet?). Example:
    L 3.1415; 
L 2.5;
*R;     // ACCU1: 7.85375 = 0x40fb51ec
T MD4;  // result: 0x40fb51ec (checked on S7-300 hardware)
TRUNC;
T MD8;  // result: 7

Currently unsupported TIA Portal specific features

  • Local FB instance call in the format of CALL <FB_name>, <local_instance_name>. Only the CALL <local_instance_name> is supported currently (as it is required in the old STEP 7 IDE).

Notes on STL semantics

  • "The STA status bit has no effect on the processing of STL statements." [Berger2005, Sec. 15.1, p. 218]
  • "When the CPU sets the OV status bit, it also always sets the OS status bit. However, while the next properly executed operation resets OV, OS remains set." (OV: Overflow, OS: Stored overflow) [Berger2005, Sec. 15.1, p. 219]
  • "S7-300 CPUs (except for CPU 318) do not load status bits /FC, STA and OR into the accumulator [with L STW]; the accumulator contains "0" at these locations." [Berger2005, Sec. 15.1, p. 220]
  • The bit logic instructions (A, AN, O, ON, X, XN) also accept the following arguments, with the meaning in the brackets after them [Berger2005, Sec. 15.3, p. 222]:
    • >0 (not CC0 and CC1)
    • >=0 (not CC0)
    • <0 (CC0 and not CC1)
    • <=0 (not CC1)
    • <>0 ((not CC0 and CC1) or (CC0 and not CC1))
    • ==0 (not CC0 and not CC1)
    • UO (CC0 and CC1)
    • OV (OV)
    • OS (OS)
    • BR (BR)
  • "You are advised to avoid data transfer [at calls] via intenal registers (for example, accumulators, address registers, RLO)" [Berger2005, Sec. 18.1.1, p. 237]

[Berger2005] Hans Berger. Automating with STEP 7 in STL and SCL. 3rd edition. Publicis, 2005. ISBN 3-89578-2743-2.

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